<?xml version="1.0"?>
<Intel_features>
  <CPUID>
    <Standard>
      <Function input="0000_0000h">
        <EAX info="Largest Standard Function Number" >
          <Decode bit="31:0" name="LFuncStd" description="Largest standard function. The largest CPUID standard-function input value supported by the processor implementation." />
        </EAX>
        <EBX info="Processor Vendor" >
          <Decode bit="31:0" name="Part1" ValueDecode="string" description="First part of the twelve 8-bit ASCII character codes form the string GenuineIntel." />
        </EBX>
        <EDX info="Processor Vendor" >
          <Decode bit="31:0" name="Part2" ValueDecode="string" description="Second part of the twelve 8-bit ASCII character codes form the string GenuineIntel." />
        </EDX>
        <ECX info="Processor Vendor" >
          <Decode bit="31:0" name="Part3" ValueDecode="string" description="Third part of the twelve 8-bit ASCII character codes form the string GenuineIntel." />
        </ECX>
      </Function>
      <Function input="0000_0001h">
        <EAX info="Processor Signature" >
          <Decode bit="27:20" name="ExtendedFamily" description="Processor extended family." />
          <Decode bit="19:16" name="ExtendedModel" description="Processor extended model." />
          <Decode bit="13:12" ValueDecode="ProcessorType" name="Type" description="Processor type." />
          <Decode bit="11:8" name="FamilyCode" description="Processor family code." />
          <Decode bit="7:4" name="ModelNumber" description="Processor model number." />
          <Decode bit="3:0" name="SteppingID" description="Processor stepping. Processor stepping (revision) for a specific model." />
        </EAX>
        <EBX info="Processors Brand ID" >
          <Decode bit="7:0" ValueDecode="ProcessorBrandID" name="BrandID" description="" />
        </EBX>
        <ECX info="Processor features" >
          <Decode bit="0" name="SSE3" description="Streaming SIMD Extensions 3. The processor supports the Streaming SIMD Extensions 3 instructions." />
          <Decode bit="2" name="DTES64" description="64-Bit Debug Store. Indicates that the processor has the ability to write a history of the 64-bit branch to and from addresses into a memory buffer." />
          <Decode bit="3" name="MONITOR" description="MONITOR/MWAIT. The processor supports the MONITOR and MWAIT instructions." />
          <Decode bit="4" name="DS-CPL" description="CPL Qualified Debug Store. The processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL." />
          <Decode bit="5" name="VMX" description="Virtual Machine Extensions. The processor supports Intel Virtualization Technology" />
          <Decode bit="6" name="SMX" description="Safer Mode Extensions. The processor supports Intel Trusted Execution Technology." />
          <Decode bit="7" name="EST" description="Enhanced Intel SpeedStep Technology. The processor implements the secondgeneration Intel SpeedStep Technology feature." />
          <Decode bit="8" name="TM2" description="Thermal Monitor 2. The processor implements the Thermal Monitor 2 thermal control circuit (TCC)." />
          <Decode bit="9" name="SSSE3" description="Supplemental Streaming SIMD Extensions 3. The processor supports the Supplemental Streaming SIMD Extensions 3 instructions." />
          <Decode bit="10" name="CNXT-ID" description="L1 Context ID. The L1 data cache mode can be set to either adaptive mode or shared mode by the BIOS." />
          <Decode bit="13" name="CX16" description="CMPXCHG16B. This processor supports the CMPXCHG16B instruction." />
          <Decode bit="14" name="xTPR" description="xTPR Update Control. The processor supports the ability to disable sending Task Priority messages. When this feature flag is set, Task Priority messages may be disabled. Bit 23 (Echo TPR disable) in the IA32_MISC_ENABLE MSR controls the sending of Task Priority messages." />
          <Decode bit="15" name="PDCM" description="Performance Capabilities MSR. The processor supports the Performance Capabilities MSR. IA32_PERF_CAPABILITIES register is MSR 345h" />
          <Decode bit="18" name="DCA" description="Direct Cache Access. The processor supports the ability to prefetch data from a memory mapped device." />
          <Decode bit="19" name="SSE4.1" description="Streaming SIMD Extensions 4.1. The processor supports the Streaming SIMD Extensions 4.1 instructions." />
          <Decode bit="20" name="SSE4.2" description="Streaming SIMD Extensions 4.2. The processor supports the Streaming SIMD Extensions 4.2 instructions." />
          <Decode bit="21" name="x2APIC" description="Extended xAPIC Support. The processor supports x2APIC feature." />
          <Decode bit="22" name="MOVBE" description="MOVBE Instruction. The processor supports MOVBE instruction." />
          <Decode bit="23" name="POPCNT" description="POPCNT Instruction. The processor supports the POPCNT instruction." />
          <Decode bit="26" name="XSAVE" description="XSAVE/XSTOR States. The processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and the XFEATURE_ENABLED_MASK register (XCR0)." />
          <Decode bit="27" name="OSXSAVE" description="A value of 1 indicates that the OS has enabled XSETBV/XGETBV instructions to access the XFEATURE_ENABLED_MASK register (XCR0), and support for processor extended state management using XSAVE/XRSTOR." />
        </ECX>
        <EDX info="Processor features" >
          <Decode bit="0" name="FPU" description="Floating-point unit on-Chip. The processor contains an FPU that supports the Intel387 floating-point instruction set." />
          <Decode bit="1" name="VME" description="Virtual Mode Extension. The processor supports extensions to virtual-8086 mode." />
          <Decode bit="2" name="DE" description="Debugging Extension. The processor supports I/O breakpoints, including the CR4.DE bit for enabling debug extensions and optional trapping of access to the DR4 and DR5 registers." />
          <Decode bit="3" name="PSE" description="Page Size Extension. The processor supports 4-Mbyte pages." />
          <Decode bit="4" name="TSC" description="Time-Stamp Counter. The RDTSC instruction is supported including the CR4.TSD bit for access/privilege control." />
          <Decode bit="5" name="MSR" description="Model Specific Registers. Model Specific Registers are implemented with the RDMSR, WRMSR instructions." />
          <Decode bit="6" name="PAE" description="Physical Address Extension. Physical addresses greater than 32 bits are supported." />
          <Decode bit="7" name="MCE" description="Machine Check Exception. Machine Check Exception, Exception 18, and the CR4.MCE enable bit are supported." />
          <Decode bit="8" name="CX8" description="CMPXCHG8 Instruction Supported. The compare and exchange 8 bytes instruction is supported." />
          <Decode bit="9" name="APIC" description="On-chip APIC Hardware Supported. The processor contains a software-accessible Local APIC." />
          <Decode bit="11" name="SEP" description="Fast System Call. Indicates whether the processor supports the Fast System Call instructions, SYSENTER and SYSEXIT. NOTE: Refer to Section 3.1.2.4 for further information regarding SYSENTER/SYSEXIT feature and SEP feature bit." />
          <Decode bit="12" name="MTRR" description="Memory Type Range Registers. The Processor supports the Memory Type Range Registers specifically the MTRR_CAP register." />
          <Decode bit="13" name="PGE" description="Page Global Enable. The global bit in the page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature." />
          <Decode bit="14" name="MCA" description="Machine Check Architecture. The Machine Check Architecture is supported, specifically the MCG_CAP register." />
          <Decode bit="15" name="CMOV" description="Conditional Move Instruction Supported. The processor supports CMOVcc, and if the FPU feature flag (bit 0) is also set, supports the FCMOVCC and FCOMI instructions." />
          <Decode bit="16" name="PAT" description="Page Attribute Table. Indicates whether the processor supports the Page Attribute Table. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on 4K granularity through a linear address." />
          <Decode bit="17" name="PSE-36" description="36-bit Page Size Extension. Indicates whether the processor supports 4-Mbyte pages that are capable of addressing physical memory beyond 4GB. This feature indicates that the upper four bits of the physical address of the 4-Mbyte page is encoded by bits 13-16 of the page directory entry." />
          <Decode bit="18" name="PSN" description="Processor serial number is present and enabled. The processor supports the 96-bit processor serial number feature, and the feature is enabled. Note: The Pentium 4 family of processors do not support this feature." />
          <Decode bit="19" name="CLFSH" description="CLFLUSH Instruction supported. Indicates that the processor supports the CLFLUSH instruction." />
          <Decode bit="21" name="DS" description="Debug Store. Indicates that the processor has the ability to write a history of the branch to and from addresses into a memory buffer." />
          <Decode bit="22" name="ACPI" description="Thermal Monitor and Software Controlled Clock Facilities supported. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control." />
          <Decode bit="23" name="MMX" description="Intel Architecture MMX technology supported. The processor supports the MMX technology instruction set extensions to Intel Architecture." />
          <Decode bit="24" name="FXSR" description="Fast floating point save and restore. Indicates whether the processor supports the FXSAVE and FXRSTOR instructions for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it uses the fast save/restore instructions." />
          <Decode bit="25" name="SSE" description="Streaming SIMD Extensions supported. The processor supports the Streaming SIMD Extensions to the Intel Architecture." />
          <Decode bit="26" name="SSE2" description="Streaming SIMD Extensions 2. Indicates the processor supports the Streaming SIMD Extensions - 2 Instructions." />
          <Decode bit="27" name="SS" description="Self-Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus." />
          <Decode bit="28" name="HTT" description="Multi-Threading. The physical processor package is capable of supporting more than one logical processor. This field does not indicate that Hyper-Threading Technology or Core Multi-Processing (CMP) has been enabled for this specific processor. To etermine if Hyper-Threading Technology or CMP is supported, compare value returned in EBX[23:16] after executing CPUID with EAX=1. If the resulting value is > 1, then the processor supports Multi-Threading. IF (CPUID(1).EBX[23:16] &gt; 1){Multi-Threading = TRUE} else {Multi-Threading = FALSE}" />
          <Decode bit="29" name="TM" description="Thermal Monitor supported. The processor implements the Thermal Monitor automatic thermal control circuit (TCC)." />
          <Decode bit="30" name="IA64" description="IA64 Capabilities. The processor is a member of the Intel Itanium processor family and currently operating in IA32 emulation mode." />
          <Decode bit="31" name="PBE" description="Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability." />
        </EDX>
        <ValueDecode id="ProcessorType" >
          <Value intput="0h" output="Original OEM processor" />
          <Value intput="1h" output="OverDrive processor" />
          <Value intput="2h" output="Dual processor" />
          <Value intput="3h" output="Intel reserved (Do Not Use)" />
        </ValueDecode>
        <ValueDecode id="ProcessorBrandID" >
          <Value intput="0h" output="Unsupported" />
          <Value intput="1h" output="Intel Celeron processor" />
          <Value intput="2h" output="Intel Pentium III processor" />
          <Value intput="3h" output="Intel Pentium III Xeon processor (If processor signature = 000006B1h, then Intel Celeron processor)" />
          <Value intput="4h" output="Intel Pentium III processor" />
          <Value intput="6h" output="Mobile Intel Pentium III Processor-M" />
          <Value intput="7h" output="Mobile Intel Celeron processor" />
          <Value intput="8h" output="Intel Pentium 4 processor (If processor signature is &gt;= 00000F13h, then Intel Genuine processor)" />
          <Value intput="9h" output="Intel Pentium 4 processor" />
          <Value intput="Ah" output="Intel Celeron Processor" />
          <Value intput="Bh" output="Intel Xeon processor (If processor signature is &lt; 00000F13h, then Intel Xeon processor MP)" />
          <Value intput="Ch" output="Intel Xeon processor MP" />
          <Value intput="Eh" output="Mobile Intel Pentium 4 processor-M (If processor signature is &lt; 00000F13h, then Intel Xeon processor)" />
          <Value intput="Fh" output="Mobile Intel Celeron processor" />
          <Value intput="11h" output="Mobile Genuine Intel processor" />
          <Value intput="12h" output="Intel Celeron M processor" />
          <Value intput="13h" output="Mobile Intel Celeron processor" />
          <Value intput="14h" output="Intel Celeron Processor" />
          <Value intput="15h" output="Mobile Genuine Intel processor" />
          <Value intput="16h" output="Intel Pentium M processor" />
          <Value intput="17h" output="Mobile Intel Celeron processor" />
          <Default output="Reserved" />
        </ValueDecode>
      </Function>
      <Function input="0000_0002h" repeadTimes="EAX#bit#7:0" >
        <EAX info="Cache or TLB Description" >
          <Decode bit="15:8" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="23:16" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="31:24" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
        </EAX>
        <EBX info="Cache or TLB Description" >
          <Decode bit="7:0" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="15:8" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="23:16" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="31:24" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
        </EBX>
        <ECX info="Cache or TLB Description" >
          <Decode bit="7:0" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="15:8" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="23:16" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="31:24" condition="bit#31==0" ValueDecode="DescriptorDecode" name="" description="" />
        </ECX>
        <EDX info="Cache or TLB Description" >
          <Decode bit="7:0" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="15:8" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="23:16" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
          <Decode bit="31:24" condition="bit#31==0" ValueDecode="DescriptorDecode" name="Cache/TLB" description="" />
        </EDX>
        <ValueDecode id="DescriptorDecode" >
          <Value intput="00h" output="Null" />
          <Value intput="01h" output="Instruction TLB: 4-KBPages, 4-way set associative, 32 entries" />
          <Value intput="02h" output="Instruction TLB: 4-MB Pages, fully associative, 2 entries" />
          <Value intput="03h" output="Data TLB: 4-KB Pages, 4-way set associative, 64 entries" />
          <Value intput="04h" output="Data TLB: 4-MB Pages, 4-way set associative, 8 entries" />
          <Value intput="05h" output="Data TLB: 4-MB Pages, 4-way set associative, 32 entries" />
          <Value intput="06h" output="1st-level instruction cache: 8-KB, 4-way set associative, 32-byte line size" />
          <Value intput="08h" output="1st-level instruction cache: 16-KB, 4-way set associative, 32-byte line size" />
          <Value intput="09h" output="1st-level Instruction Cache: 32-KB, 4-way set associative, 64-byte line size" />
          <Value intput="0Ah" output="1st-level data cache: 8-KB, 2-way set associative, 32-byte line size" />
          <Value intput="0Ch" output="1st-level data cache: 16-KB, 4-way set associative, 32-byte line size" />
          <Value intput="0Dh" output="1st-level Data Cache: 16-KB, 4-way set associative, 64-byte line size, ECC" />
          <Value intput="21h" output="256-KB L2 (MLC), 8-way set associative, 64-byte line size" />
          <Value intput="22h" output="3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64-byte line size" />
          <Value intput="23h" output="3rd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="25h" output="3rd-level cache: 2-MB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="29h" output="3rd-level cache: 4-MB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="2Ch" output="1st-level data cache: 32-KB, 8-way set associative, 64-byte line size" />
          <Value intput="30h" output="1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size" />
          <Value intput="39h" output="2nd-level cache: 128-KB, 4-way set associative, sectored cache, 64-byte line size" />
          <Value intput="3Ah" output="2nd-level cache: 192-KB, 6-way set associative, sectored cache, 64-byte line size" />
          <Value intput="3Bh" output="2nd-level cache: 128-KB, 2-way set associative, sectored cache, 64-byte line size" />
          <Value intput="3Ch" output="2nd-level cache: 256-KB, 4-way set associative, sectored cache, 64-byte line size" />
          <Value intput="3Dh" output="2nd-level cache: 384-KB, 6-way set associative, sectored cache, 64-byte line size" />
          <Value intput="3Eh" output="2nd-level cache: 512-KB, 4-way set associative, sectored cache, 64-byte line size" />
          <Value intput="40h" output="No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" />
          <Value intput="41h" output="2nd-level cache: 128-KB, 4-way set associative, 32-byte line size" />
          <Value intput="42h" output="2nd-level cache: 256-KB, 4-way set associative, 32-byte line size" />
          <Value intput="43h" output="2nd-level cache: 512-KB, 4-way set associative, 32-byte line size" />
          <Value intput="44h" output="2nd-level cache: 1-MB, 4-way set associative, 32-byte line size" />
          <Value intput="45h" output="2nd-level cache: 2-MB, 4-way set associative, 32-byte line size" />
          <Value intput="46h" output="3rd-level cache: 4MB, 4-way set associative, 64-byte line size" />
          <Value intput="47h" output="3rd-level cache: 8MB, 8-way set associative, 64-byte line size" />
          <Value intput="49h" output="3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h) 2nd-level cache: 4MB, 16-way set associative, 64-byte line size" />
          <Value intput="4Ah" output="3rd-level cache: 6MB, 12-way set associative, 64-byte line size" />
          <Value intput="4Bh" output="3rd-level cache: 8MB, 16-way set associative, 64-byte line size" />
          <Value intput="4Ch" output="3rd-level cache: 12MB, 12-way set associative, 64-byte line size" />
          <Value intput="4Dh" output="3rd-level cache: 16MB, 16-way set associative, 64-byte line size" />
          <Value intput="4Eh" output="2nd-level cache: 6MB, 24-way set associative, 64-byte line size" />
          <Value intput="50h" output="Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries" />
          <Value intput="51h" output="Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries" />
          <Value intput="52h" output="Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 256 entries" />
          <Value intput="55h" output="Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries" />
          <Value intput="56h" output="L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries" />
          <Value intput="57h" output="L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries" />
          <Value intput="5Ah" output="Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries" />
          <Value intput="5Bh" output="Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries" />
          <Value intput="5Ch" output="Data TLB: 4-KB or 4-MB pages, fully associative, 128 entries" />
          <Value intput="5Dh" output="Data TLB: 4-KB or 4-MB pages, fully associative, 256 entries" />
          <Value intput="60h" output="1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="66h" output="1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size" />
          <Value intput="67h" output="1st-level data cache: 16-KB, 4-way set associative, sectored cache, 64-byte line size" />
          <Value intput="68h" output="1st-level data cache: 32-KB, 4 way set associative, sectored cache, 64-byte line size" />
          <Value intput="70h" output="Trace cache: 12K-uops, 8-way set associative" />
          <Value intput="71h" output="Trace cache: 16K-uops, 8-way set associative" />
          <Value intput="72h" output="Trace cache: 32K-uops, 8-way set associative" />
          <Value intput="73h" output="Trace cache: 64K-uops, 8-way set associative" />
          <Value intput="78h" output="2nd-level cache: 1-MB, 4-way set associative, 64-byte line size" />
          <Value intput="79h" output="2nd-level cache: 128-KB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="7Ah" output="2nd-level cache: 256-KB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="7Bh" output="2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="7Ch" output="2nd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size" />
          <Value intput="7Dh" output="2nd-level cache: 2-MB, 8-way set associative, 64-byte line size" />
          <Value intput="7Fh" output="2nd-level cache: 512-KB, 2-way set associative, 64-byte line size" />
          <Value intput="82h" output="2nd-level cache: 256-KB, 8-way set associative, 32-byte line size" />
          <Value intput="83h" output="2nd-level cache: 512-KB, 8-way set associative, 32-byte line size" />
          <Value intput="84h" output="2nd-level cache: 1-MB, 8-way set associative, 32-byte line size" />
          <Value intput="85h" output="2nd-level cache: 2-MB, 8-way set associative, 32-byte line size" />
          <Value intput="86h" output="2nd-level cache: 512-KB, 4-way set associative, 64-byte line size" />
          <Value intput="87h" output="2nd-level cache: 1-MB, 8-way set associative, 64-byte line size" />
          <Value intput="B0h" output="Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries" />
          <Value intput="B1h" output="Instruction TLB: 4-MB Pages, 4-way set associative, 4 entries" />
          <Value intput="B2h" output=" Instruction TLB: 2-MB Pages, 4-way set associative, 8 entries" />
          <Value intput="B3h" output="Data TLB: 4-KB Pages, 4-way set associative, 128 entries" />
          <Value intput="B4h" output="Data TLB: 4-KB Pages, 4-way set associative, 256 entries" />
          <Value intput="CAh" output="Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries" />
          <Value intput="D0h" output="512KB L3 Cache, 4-way set associative, 64-byte line size" />
          <Value intput="D1h" output="1-MB L3 Cache, 4-way set associative, 64-byte line size" />
          <Value intput="D2h" output="2-MB L3 Cache, 4-way set associative, 64-byte line size" />
          <Value intput="D6h" output="1-MB L3 Cache, 8-way set associative, 64-byte line size" />
          <Value intput="D7h" output="2-MB L3 Cache, 8-way set associative, 64-byte line size" />
          <Value intput="D8h" output="4-MB L3 Cache, 8-way set associative, 64-byte line size" />
          <Value intput="DCh" output="2-MB L3 Cache, 12-way set associative, 64-byte line size" />
          <Value intput="DDh" output="4-MB L3 Cache, 12-way set associative, 64-byte line size" />
          <Value intput="DEh" output="8-MB L3 Cache, 12-way set associative, 64-byte line size" />
          <Value intput="E2h" output="2-MB L3 Cache, 16-way set associative, 64-byte line size" />
          <Value intput="E3h" output="4-MB L3 Cache, 16-way set associative, 64-byte line size" />
          <Value intput="E4h" output="8-MB L3 Cache, 16-way set associative, 64-byte line size" />
          <Value intput="F0h" output="64-byte Prefetching" />
          <Value intput="F1h" output="128-byte Prefetching" />
          <Default output="Unknown" />
        </ValueDecode>
      </Function>
      <Function input="0000_0004h">
        <EAX info="Deterministic Cache Parameters" >
          <Decode bit="31:26" increment="1" name="Cores" description="Maximum number of processor cores per package." />
          <Decode bit="25:14" increment="1" name="Threads" description="Maximum number of threads sharing this cache." />
          <Decode bit="9" name="FACache" description="Fully Associative Cache" />
          <Decode bit="8" name="SICacheLevel" description="Self Initializing cache level" />
          <Decode bit="7:5" name="CacheLevel" description="Cache Level (Starts at 1)" />
          <Decode bit="4:0" name="CacheType" ValueDecode="CacheType" description="Cache Type" />
        </EAX>
        <EBX info="Deterministic Cache Parameters" >
          <Decode bit="31:22" increment="1" name="Ways" description="Ways of Associativity." />
          <Decode bit="21:12" increment="1" name="Partitions" description="Physical Line partitions." />
          <Decode bit="11:0" name="LineSize" description="System Coherency Line Size." />
        </EBX>
        <ECX info="Deterministic Cache Parameters" >
          <Decode bit="31:0" increment="1" name="Sets" description="Number of Sets" />
        </ECX>
        <EDX info="Deterministic Cache Parameters" >
          <Decode bit="9:0" increment="1" name="Stride" description="Prefetch stride (64B if this field is 0)" />
        </EDX>
        <ValueDecode id="CacheType" >
          <Value intput="0" output="Null, no more caches" />
          <Value intput="1" output="Data Cache" />
          <Value intput="2" output="Instruction Cache" />
          <Value intput="3" output="Unified Cache" />
          <Default output="Reserved" />
        </ValueDecode>
      </Function>
      <Function input="0000_0005h">
        <EAX info="MONITOR / MWAIT Parameters" >
          <Decode bit="15:0" name="MinSize" description="Smallest monitor line size in bytes." />
        </EAX>
        <EBX info="MONITOR / MWAIT Parameters" >
          <Decode bit="15:0" name="MaxSize" description="Largest monitor line size in bytes." />
        </EBX>
        <ECX info="MONITOR / MWAIT Parameters" >
          <Decode bit="1" name="Interrupts" description="Support for treating interrupts as break-events for MWAIT." />
          <Decode bit="0" name="Extension" description="MONITOR / MWAIT Extensions supported" />
        </ECX>
        <EDX info="MONITOR / MWAIT Parameters" >
          <Decode bit="3:0" name="SubStates0" description="Number of C0 sub-states supported using MONITOR / MWAIT" />
          <Decode bit="7:4" name="SubStates1" description="Number of C1 sub-states supported using MONITOR / MWAIT" />
          <Decode bit="11:8" name="SubStates2" description="Number of C2 sub-states supported using MONITOR / MWAIT (C2 sub-states supported on processors prior to the Core i7 generation)" />
          <Decode bit="15:12" name="SubStates3" description="Number of C3 sub-states supported using MONITOR / MWAIT. On Core i7 and subsequent processors: Number of C6 sub-states supported using MONITOR / MWAIT" />
          <Decode bit="19:16" name="SubStates4" description="Number of C4 sub-states supported using MONITOR / MWAIT. On Core i7 and subsequent processors: Number of C7 sub-states supported using MONITOR / MWAIT" />
        </EDX>
      </Function>
      <Function input="0000_0006h">
        <EAX info="Digital Thermal Sensor" >
          <Decode bit="0" name="ThermalSensor" description="Digital Thermal Sensor Capability" />
          <Decode bit="1" name="TurboBoost" description="Intel Turbo Boost Technology" />
        </EAX>
        <EBX info="Power Management Parameters" >
          <Decode bit="3:0" name="IThresholds" description="Number of Interrupt Thresholds." />
        </EBX>
        <ECX info="Power Management Parameters" >
          <Decode bit="0" name="Feedback" description="Hardware Coordination Feedback Capability (Presence of ACNT, MCNT MSRs)" />
        </ECX>
        <EDX>
        </EDX>
      </Function>
      <Function input="0000_0009h">
        <EAX info="Direct Cache Access (DCA) Parameters" >
          <Decode bit="31:0" name="PLATFORM_DCA_CAP" description="Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)" />
        </EAX>
        <EBX>
        </EBX>
        <ECX>
        </ECX>
        <EDX>
        </EDX>
      </Function>
      <Function input="0000_000Ah">
        <EAX info="Performance Monitor Features" >
          <Decode bit="31:24" name="SizeEBX" description="Length of EBX bit vector to enumerate architectural performance monitoring events" />
          <Decode bit="23:16" name="BWGPPMC" description="Bit width of general-purpose, performance monitoring counter" />
          <Decode bit="15:8" name="NrGPPMC" description="Number of general-purpose performance monitoring counter per logical processor" />
          <Decode bit="7:0" name="VersionID" description="Version ID of architectural performance monitoring" />
        </EAX>
        <EBX info="Performance Monitor Features" >
          <Decode bit="6" name="BMRE" description="Branch mispredict retired event not available if 1" />
          <Decode bit="5" name="BIRE" description="Branch instruction retired event not available if 1" />
          <Decode bit="4" name="LLCME" description="Last-level cache misses event not available if 1" />
          <Decode bit="3" name="LLCRE" description="Last-level cache reference event not available if 1" />
          <Decode bit="2" name="RCE" description="Reference cycles event not available if 1" />
          <Decode bit="1" name="IRE" description="Instruction retired event not available if 1" />
          <Decode bit="0" name="CCE" description="Core cycle event not available if 1" />
        </EBX>
        <ECX>
        </ECX>
        <EDX info="Performance Monitor Features" >
          <Decode bit="12:5" name="BWFFPC" description="Bit width of fixed-function performance counters (if Version ID &gt; 1)" />
          <Decode bit="4:0" name="NrFFPC" description="Number of fixed-function performance counters (if Version ID &gt; 1)" />
        </EDX>
      </Function>
      <Function input="0000_000Dh">
        <EAX info="XSAVE Features" >
          <Decode bit="31:0" name="BitFields" description="Reports the valid bit fields of the lower 32 bits of the XFEATURE_ENABLED_MASK register (XCR0). If a bit is 0, the corresponding bit field in XCR0 is reserved." />
        </EAX>
        <EBX info="XSAVE Features" >
          <Decode bit="31:0" name="MaxSize" description="Maximum size (bytes) required by enabled features in XFEATURE_ENABLED_MASK (XCR0). May be different than ECX when features at the end of the save area are not enabled." />
        </EBX>
        <ECX info="XSAVE Features">
          <Decode bit="31:0" name="MaxSize" description="Maximum size (bytes) of the XSAVE/XRSTOR save area required by all supported features in the processor, i.e all the valid bit fields in XFEATURE_ENABLED_MASK. This includes the size needed for the XSAVE.HEADER." />
        </ECX>
        <EDX info="XSAVE Features" >
          <Decode bit="31:0" name="BitFields" description="Reports the valid bit fields of the upper 32 bits of the XFEATURE_ENABLED_MASK register (XCR0). If a bit is 0, the corresponding bit field in XCR0 is reserved." />
        </EDX>
      </Function>
    </Standard>
    <Extended>
      <Function input="8000_0000h">
        <EAX info="Largest Extended Function Number" >
          <Decode bit="31:0" name="LFuncExt" description="Largest extended function. The largest CPUID extended-function input value supported by the processor implementation." />
        </EAX>
        <EBX>
        </EBX>
        <ECX>
        </ECX>
        <EDX>
        </EDX>
      </Function>
      <Function input="8000_0001h">
        <EAX>
        </EAX>
        <EBX>
        </EBX>
        <ECX info="Processor extended features" >
          <Decode bit="0" name="LAHF" description="LAHF / SAHF. A value of 1 indicates the LAHF and SAHF instructions are available when the IA-32e mode is enabled and the processor is operating in the 64-bit sub-mode." />
        </ECX>
        <EDX info="Processor extended features" >
          <Decode bit="11" name="SYSCALL" description="SYSCALL/SYSRET. The processor supports the SYSCALL and SYSRET instructions." />
          <Decode bit="20" name="XD Bit" description="Execution Disable Bit" />
          <Decode bit="29" name="Intel 64" description="Intel 64 Instruction Set Architecture. The processor supports Intel 64 Architecture extensions to the IA-32 Architecture." />
        </EDX>
      </Function>
      <Function input="8000_0002h">
        <EAX info="Processor Name">
          <Decode bit="31:0" name="Part1" ValueDecode="string" description="Processor Name String Identifier" />
        </EAX>
        <EBX info="Processor Name">
          <Decode bit="31:0" name="Part2" ValueDecode="string" description="Processor Name String Identifier" />
        </EBX>
        <ECX info="Processor Name" >
          <Decode bit="31:0" name="Part3" ValueDecode="string" description="Processor Name String Identifier" />
        </ECX>
        <EDX info="Processor Name" >
          <Decode bit="31:0" name="Part4" ValueDecode="string" description="Processor Name String Identifier" />
        </EDX>
      </Function>
      <Function input="8000_0003h">
        <EAX info="Processor Name">
          <Decode bit="31:0" name="Part5" ValueDecode="string" description="Processor Name String Identifier" />
        </EAX>
        <EBX info="Processor Name">
          <Decode bit="31:0" name="Part6" ValueDecode="string" description="Processor Name String Identifier" />
        </EBX>
        <ECX info="Processor Name" >
          <Decode bit="31:0" name="Part7" ValueDecode="string" description="Processor Name String Identifier" />
        </ECX>
        <EDX info="Processor Name" >
          <Decode bit="31:0" name="Part8" ValueDecode="string" description="Processor Name String Identifier" />
        </EDX>
      </Function>
      <Function input="8000_0004h">
        <EAX info="Processor Name">
          <Decode bit="31:0" name="Part9" ValueDecode="string" description="Processor Name String Identifier" />
        </EAX>
        <EBX info="Processor Name">
          <Decode bit="31:0" name="Part10" ValueDecode="string" description="Processor Name String Identifier" />
        </EBX>
        <ECX info="Processor Name" >
          <Decode bit="31:0" name="Part11" ValueDecode="string" description="Processor Name String Identifier" />
        </ECX>
        <EDX info="Processor Name" >
          <Decode bit="31:0" name="Part12" ValueDecode="string" description="Processor Name String Identifier" />
        </EDX>
      </Function>
      <Function input="8000_0006h">
        <EAX>
        </EAX>
        <EBX>
        </EBX>
        <ECX info="Extended L2 Cache Features" >
          <Decode bit="31:16" name="L2CacheSize1024" description="L2 Cache size described in 1024-byte units." />
          <Decode bit="15:12" ValueDecode="CacheAssociativity" name="L2CacheAssoc" description="L2 Cache Associativity" />
          <Decode bit="7:0" name="L2CacheLineSize" description="L2 Cache Line Size in bytes." />
        </ECX>
        <EDX>
        </EDX>
        <ValueDecode id="CacheAssociativity" >
          <Value intput="0h" output="Disabled" />
          <Value intput="1h" output="Direct mapped" />
          <Value intput="2h" output="2-Way" />
          <Value intput="4h" output="4-Way" />
          <Value intput="6h" output="8-Way" />
          <Value intput="8h" output="16-Way" />
          <Value intput="Fh" output="Fully associative" />
          <Defaut output="Unknown" />
        </ValueDecode>
      </Function>
      <Function input="8000_0007h">
        <EAX>
        </EAX>
        <EBX>
        </EBX>
        <ECX>
        </ECX>
        <EDX info="Power Management Details">
          <Decode bit="8:0" name="TSC_Invariance" description="TSC Invariance (1 = Available, 0 = Not available) TSC will run at a constant rate in all ACPI P-states, C-states and T-states." />
        </EDX>
      </Function>
      <Function input="8000_0008h">
        <EAX info="Virtual and Physical Address Size Definitions" >
          <Decode bit="15:8" name="VirtAddrSize" description="Virtual Address Size: Number of address bits supported by the processor for a virtual address." />
          <Decode bit="7:0" name="PhysAddrSize" description="Physical Address Size: Number of address bits supported by the processor for a physical address." />
        </EAX>
        <EBX>
        </EBX>
        <ECX>
        </ECX>
        <EDX>
        </EDX>
      </Function>
    </Extended>
  </CPUID>
</Intel_features>