<?xml version="1.0"?>
<AMD_features>
  <CPUID>
    <Standard>
      <Function input="0000_0000h">
        <EAX info="Largest Standard Function Number" >
          <Decode bit="31:0" name="LFuncStd" description="Largest standard function. The largest CPUID standard-function input value supported by the processor implementation." />
        </EAX>
        <EBX info="Processor Vendor" >
          <Decode bit="31:0" name="Vendor" ValueDecode="string" description="First part of the twelve 8-bit ASCII character codes form the string AuthenticAMD." />
        </EBX>
        <EDX info="Processor Vendor" >
          <Decode bit="31:0" name="Vendor" ValueDecode="string" description="Second part of the twelve 8-bit ASCII character codes form the string AuthenticAMD." />
        </EDX>
        <ECX info="Processor Vendor" >
          <Decode bit="31:0" name="Vendor" ValueDecode="string" description="Third part of the twelve 8-bit ASCII character codes form the string AuthenticAMD." />
        </ECX>
      </Function>
      <Function input="0000_0001h">
        <EAX info="Family, Model, Stepping Identifiers" >
          <Decode bit="27:20" name="ExtendedFamily" description="Processor extended family." />
          <Decode bit="19:16" name="ExtendedModel" description="Processor extended model." />
          <Decode bit="11:8" name="BaseFamily" description="Base processor family." />
          <Decode bit="7:4" name="BaseModel" description="Base processor model." />
          <Decode bit="3:0" name="Stepping" description="Processor stepping. Processor stepping (revision) for a specific model." />
        </EAX>
        <EBX info="LocalApicId, LogicalProcessorCount, CLFlush" >
          <Decode bit="31:24" name="LocalApicId" description="Initial local APIC physical ID. The 8-bit value assigned to the local APIC physical ID register at power-up. Some of the bits of LocalApicId represent the CPU core within a processor and other bits represent the processor ID." />
          <Decode bit="23:16" name="LogicalProcessorCount" description="logical processor count." />
          <Decode bit="15:8" name="CLFlush" description="CLFLUSH size. Specifies the size of a cache line in quadwords flushed by the CLFLUSH instruction." />
          <Decode bit="7:0" name="8BitBrandId" description="8-bit brand ID. This field, in conjunction with CPUID Fn8000_0001_EBX[BrandId], is used by the BIOS to generate the processor name string." />
        </EBX>
        <ECX info="Feature Identifiers" >
          <Decode bit="23" name="POPCNT" description="POPCNT instruction." />
          <Decode bit="19" name="SSE41" description="SSE4.1 instruction support." />
          <Decode bit="13" name="CMPXCHG16B" description="CMPXCHG16B instruction." />
          <Decode bit="9" name="SSSE3" description="Supplemental SSE3 extensions." />
          <Decode bit="3" name="MONITOR" description="MONITOR/MWAIT instructions." />
          <Decode bit="0" name="SSE3" description="SSE3 extensions." />
        </ECX>
        <EDX info="Feature Identifiers" >
          <Decode bit="28" name="HTT" description="Hyper-threading technology. Indicates either that there is more than one thread per CPU core or more than one CPU core per processor." />
          <Decode bit="26" name="SSE2" description="SSE2 extensions." />
          <Decode bit="25" name="SSE" description="SSE extensions." />
          <Decode bit="24" name="FXSR" description="FXSAVE and FXRSTOR instructions." />
          <Decode bit="23" name="MMX" description="MMX instructions." />
          <Decode bit="19" name="CLFSH" description="CLFLUSH instruction." />
          <Decode bit="17" name="PSE36" description="Page-size extensions. The PDE[20:13] supplies physical address [39:32]." />
          <Decode bit="16" name="PAT" description="Page attribute table." />
          <Decode bit="15" name="CMOV" description="Conditional move instructions." />
          <Decode bit="14" name="MCA" description="Machine check architecture." />
          <Decode bit="13" name="PGE" description="Page global extension." />
          <Decode bit="12" name="MTRR" description="Memory-type range registers." />
          <Decode bit="11" name="SysEnterSysExit" description="SYSENTER and SYSEXIT instructions." />
          <Decode bit="9" name="APIC" description="Advanced programmable interrupt controller. Indicates APIC exists and is enabled." />
          <Decode bit="8" name="CMPXCHG8B" description="CMPXCHG8B instruction." />
          <Decode bit="7" name="MCE" description="Machine check exception" />
          <Decode bit="6" name="PAE" description="Physical-address extensions. Indicates support for physical addresses &gt;= 32b. Number of physical address bits above 32b is implementation specific." />
          <Decode bit="5" name="MSR" description="AMD model-specific registers. Indicates support for AMD model-specific registers (MSRs), with RDMSR and WRMSR instructions." />
          <Decode bit="4" name="TSC" description="Time stamp counter. RDTSC and RDTSCP instruction support." />
          <Decode bit="3" name="PSE" description="Page-size extensions." />
          <Decode bit="2" name="DE" description="Debugging extensions." />
          <Decode bit="1" name="VME" description="Virtual-mode enhancements. CR4.VME, CR4.PVI, software interrupt indirection, expansion of the TSS with the software, indirection bitmap, EFLAGS.VIF, EFLAGS.VIP." />
          <Decode bit="0" name="FPU" description="x87 floating point unit on-chip." />
        </EDX>
      </Function>
      <Function input="0000_0005h">
        <EAX info="MONITOR/MWAIT" >
          <Decode bit="15:0" name="MonLineSizeMin" description="Smallest monitor-line size in bytes." />
        </EAX>
        <EBX info="MONITOR/MWAIT" >
          <Decode bit="15:0" name="MonLineSizeMax" description="Largest monitor-line size in bytes." />
        </EBX>
        <ECX info="MONITOR/MWAIT" >
          <Decode bit="1" name="IBE" description="Indicates MWAIT can use ECX bit 0 to allow interrupts to cause an exit from the monitor event pending state, even if EFLAGS.IF=0." />
          <Decode bit="0" name="EMX" description="Indicates enumeration MONITOR/MWAIT extensions are supported." />
        </ECX>
        <EDX>
        </EDX>
      </Function>
    </Standard>
    <Extended>
      <Function input="8000_0000h">
        <EAX info="Largest Extended Function Number" >
          <Decode bit="31:0" name="LFuncExt" description="Largest extended function. The largest CPUID extended-function input value supported by the processor implementation." />
        </EAX>
        <EBX info="Processor Vendor" >
          <Decode bit="31:0" name="Vendor" ValueDecode="string" description="First part of the twelve 8-bit ASCII character codes form the string AuthenticAMD." />
        </EBX>
        <EDX info="Processor Vendor" >
          <Decode bit="31:0" name="Vendor" ValueDecode="string" description="Second part of the twelve 8-bit ASCII character codes form the string AuthenticAMD." />
        </EDX>
        <ECX info="Processor Vendor" >
          <Decode bit="31:0" name="Vendor" ValueDecode="string" description="Third part of the twelve 8-bit ASCII character codes form the string AuthenticAMD." />
        </ECX>
      </Function>
      <Function input="8000_0001h">
        <EAX info="Family, Model, Stepping Identifiers" >
          <Decode bit="27:20" name="ExtendedFamily" description="Processor extended family." />
          <Decode bit="19:16" name="ExtendedModel" description="Processor extended model." />
          <Decode bit="11:8" name="BaseFamily" description="Base processor family." />
          <Decode bit="7:4" name="BaseModel" description="Base processor model." />
          <Decode bit="3:0" name="Stepping" description="Processor stepping. Processor stepping (revision) for a specific model." />
        </EAX>
        <EBX info="BrandId Identifier" >
          <Decode bit="31:28" name="PkgType" description="If (Family[7:0] &gt;= 10h) then the definition of PkgType is contained in the processor BKDG. If (Family[7:0] &lt; 10h) then the definition of PkgType is reserved." />
          <Decode bit="15:0" name="BrandId" description="brand ID. This field, in conjunction with CPUID Fn0000_0001_EBX[8BitBrandId], is used by BIOS to generate the processor name string." />
        </EBX>
        <ECX info="Feature Identifiers" >
          <Decode bit="13" name="WDT" description="Watchdog timer support." />
          <Decode bit="12" name="SKINIT" description="SKINIT and STGI are supported, independent of the value of MSRC000_0080[SVME]." />
          <Decode bit="11" name="SSE5" description="SSE5 Instruction support." />
          <Decode bit="10" name="IBS" description="Instruction based sampling." />
          <Decode bit="9" name="OSVW" description="OS visible workaround. Indicates OS-visible workaround support." />
          <Decode bit="8" name="3DNowPrefetch" description="PREFETCH and PREFETCHW instruction support." />
          <Decode bit="7" name="MisAlignSse" description="Misaligned SSE mode." />
          <Decode bit="6" name="SSE4A" description="EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support." />
          <Decode bit="5" name="ABM" description="Advanced bit manipulation. LZCNT instruction support." />
          <Decode bit="4" name="AltMovCr8" description="LOCK MOV CR0 means MOV CR8." />
          <Decode bit="3" name="ExtApicSpace" description="Extended APIC space. This bit indicates the presence of extended APIC register space starting at offset 400h from the APIC Base Address Register, as specified in the BKDG." />
          <Decode bit="2" name="SVM" description="Secure virtual machine." />
          <Decode bit="1" name="CmpLegacy" description="Core multi-processing legacy mode." />
          <Decode bit="0" name="LahfSahf" description="LAHF and SAHF instruction support in 64-bit mode." />
        </ECX>
        <EDX info="Feature Identifiers" >
          <Decode bit="31" name="3DNow" description="3DNow! instructions." />
          <Decode bit="30" name="3DNowExt" description="AMD extensions to 3DNow! instructions." />
          <Decode bit="29" name="LM" description="Long mode." />
          <Decode bit="27" name="RDTSCP" description="RDTSCP instruction." />
          <Decode bit="26" name="Page1GB" description="1-GB large page support." />
          <Decode bit="25" name="FFXSR" description="FXSAVE and FXRSTOR instruction optimizations." />
          <Decode bit="24" name="FXSR" description="FXSAVE and FXRSTOR instructions. Same as CPUID Fn0000_0001_EDX[FXSR]." />
          <Decode bit="23" name="MMX" description="MMX instructions. Same as CPUID Fn0000_0001_EDX[MMX]." />
          <Decode bit="22" name="MmxExt" description="AMD extensions to MMX instructions." />
          <Decode bit="20" name="NX" description="No-execute page protection." />
          <Decode bit="17" name="PSE36" description="Page-size extensions. Same as CPUID Fn0000_0001_EDX[PSE36]." />
          <Decode bit="16" name="PAT" description="Page attribute table. Same as CPUID Fn0000_0001_EDX[PAT]." />
          <Decode bit="15" name="CMOV" description="Conditional move instructions. Same as CPUID Fn0000_0001_EDX[CMOV]." />
          <Decode bit="14" name="MCA" description="Machine check architecture. Same as CPUID Fn0000_0001_EDX[MCA]." />
          <Decode bit="13" name="PGE" description="Page global extension. Same as CPUID Fn0000_0001_EDX[PGE]." />
          <Decode bit="12" name="MTRR" description="Memory-type range registers. Same as CPUID Fn0000_0001_EDX[MTRR]." />
          <Decode bit="11" name="SysCallSysRet" description="SYSCALL and SYSRET instructions." />
          <Decode bit="9" name="APIC" description="Advanced programmable interrupt controller. Same as CPUID Fn0000_0001_EDX[APIC]." />
          <Decode bit="8" name="CMPXCHG8B" description="CMPXCHG8B instruction. Same as CPUID Fn0000_0001_EDX[CMPXCHG8B]." />
          <Decode bit="7" name="MCE" description="Machine check exception. Same as CPUID Fn0000_0001_EDX[MCE]." />
          <Decode bit="6" name="PAE" description="Physical-address extensions. Same as CPUID Fn0000_0001_EDX[PAE]." />
          <Decode bit="5" name="MSR" description="AMD model-specific registers. Same as CPUID Fn0000_0001_EDX[MSR]." />
          <Decode bit="4" name="TSC" description="Time stamp counter. Same as CPUID Fn0000_0001_EDX[TSC]." />
          <Decode bit="3" name="PSE" description="Page-size extensions. Same as CPUID Fn0000_0001_EDX[PSE]." />
          <Decode bit="2" name="DE" description="Debugging extensions. Same as CPUID Fn0000_0001_EDX[DE]." />
          <Decode bit="1" name="VME" description="Virtual-mode enhancements. Same as CPUID Fn0000_0001_EDX[VME]." />
          <Decode bit="1" name="FPU" description="x87 floating-point unit on-chip. Same as CPUID Fn0000_0001_EDX[FPU]." />
        </EDX>
      </Function>
      <Function input="8000_0002h">
        <EAX info="Processor Name">
          <Decode bit="31:0" name="Part1" ValueDecode="string" description="Processor Name String Identifier" />
        </EAX>
        <EBX info="Processor Name">
          <Decode bit="31:0" name="Part2" ValueDecode="string" description="Processor Name String Identifier" />
        </EBX>
        <ECX info="Processor Name" >
          <Decode bit="31:0" name="Part3" ValueDecode="string" description="Processor Name String Identifier" />
        </ECX>
        <EDX info="Processor Name" >
          <Decode bit="31:0" name="Part4" ValueDecode="string" description="Processor Name String Identifier" />
        </EDX>
      </Function>
      <Function input="8000_0003h">
        <EAX info="Processor Name">
          <Decode bit="31:0" name="Part5" ValueDecode="string" description="Processor Name String Identifier" />
        </EAX>
        <EBX info="Processor Name">
          <Decode bit="31:0" name="Part6" ValueDecode="string" description="Processor Name String Identifier" />
        </EBX>
        <ECX info="Processor Name" >
          <Decode bit="31:0" name="Part7" ValueDecode="string" description="Processor Name String Identifier" />
        </ECX>
        <EDX info="Processor Name" >
          <Decode bit="31:0" name="Part8" ValueDecode="string" description="Processor Name String Identifier" />
        </EDX>
      </Function>
      <Function input="8000_0004h">
        <EAX info="Processor Name">
          <Decode bit="31:0" name="Part9" ValueDecode="string" description="Processor Name String Identifier" />
        </EAX>
        <EBX info="Processor Name">
          <Decode bit="31:0" name="Part10" ValueDecode="string" description="Processor Name String Identifier" />
        </EBX>
        <ECX info="Processor Name" >
          <Decode bit="31:0" name="Part11" ValueDecode="string" description="Processor Name String Identifier" />
        </ECX>
        <EDX info="Processor Name" >
          <Decode bit="31:0" name="Part12" ValueDecode="string" description="Processor Name String Identifier" />
        </EDX>
      </Function>
      <Function input="8000_0005h">
        <EAX info="L1 TLB Identifiers" >
          <Decode bit="31:24" ValueDecode="AssociativityFields" name="L1DTlb2and4MAssoc" description="Data TLB associativity for 2-MB and 4-MB pages." />
          <Decode bit="23:16" name="L1DTlb2and4MSize" description="Data TLB number of entries for 2-MB and 4-MB pages. The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value." />
          <Decode bit="15:8" name="L1ITlb2and4MAssoc" description="Instruction TLB associativity for 2-MB and 4-MB pages." />
          <Decode bit="7:0" name="L1ITlb2and4MSize" description="Instruction TLB number of entries for 2-MB and 4-MB pages. The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value." />
        </EAX>
        <EBX info="L1 TLB Identifiers" >
          <Decode bit="31:24" ValueDecode="AssociativityFields" name="L1DTlb4KAssoc" description="Data TLB associativity for 4 KB pages." />
          <Decode bit="23:16" name="L1DTlb4KSize" description="Data TLB number of entries for 4 KB pages." />
          <Decode bit="15:8" name="L1ITlb4KAssoc" description="Instruction TLB associativity for 4 KB pages." />
          <Decode bit="7:0" name="L1ITlb4KSize" description="Instruction TLB number of entries for 4 KB pages." />
        </EBX>
        <ECX info="L1 Cache Identifiers" >
          <Decode bit="31:24" name="L1DcSize" description="L1 data cache size in KB." />
          <Decode bit="23:16" ValueDecode="AssociativityFields" name="L1DcAssoc" description="L1 data cache associativity." />
          <Decode bit="15:8" name="L1DcLinesPerTag" description="L1 data cache lines per tag." />
          <Decode bit="7:0" name="L1DcLineSize" description="L1 data cache line size in bytes." />
        </ECX>
        <EDX info="L1 Cache Identifiers" >
          <Decode bit="31:24" name="L1IcSize" description="L1 instruction cache size KB." />
          <Decode bit="23:16" ValueDecode="AssociativityFields" name="L1IcAssoc" description="L1 instruction cache associativity." />
          <Decode bit="15:8" name="L1IcLinesPerTag" description="L1 instruction cache lines per tag." />
          <Decode bit="7:0" name="L1IcLineSize" description="L1 instruction cache line size in bytes." />
        </EDX>
        <ValueDecode id="AssociativityFields" >
          <Value intput="00h" output="Reserved" />
          <Value intput="01h" output="Direct mapped" />
          <Value intput="02h:FEh" output="Associativity" />
          <Value intput="FFh" output="Fully associative" />
          <Defaut output="Reserved" />
        </ValueDecode>
      </Function>
      <Function input="8000_0006h">
        <EAX info="L2 TLB Identifiers" >
          <Decode bit="31:28" ValueDecode="AssociativityFields" name="L2DTlb2and4MAssoc" description="L2 data TLB associativity for 2-MB and 4-MB pages." />
          <Decode bit="27:16" name="L2DTlb2and4MSize" description="L2 data TLB number of entries for 2-MB and 4-MB pages. The value returned is for the number of entries available for the 2-MB page size; 4-MB pages require two 2-MB entries, so the number of entries available for the 4-MB page size is one-half the returned value." />
          <Decode bit="15:12" ValueDecode="AssociativityFields" name="L2ITlb2and4MAssoc" description="L2 instruction TLB associativity for 2-MB and 4-MB pages." />
          <Decode bit="11:0" name="L2ITlb2and4MSize" description="L2 instruction TLB associativity for 2-MB and 4-MB pages." />
        </EAX>
        <EBX info="L2 TLB Identifiers" >
          <Decode bit="31:28" ValueDecode="AssociativityFields" name="L2DTlb4KAssoc" description="L2 data TLB associativity for 4-KB pages." />
          <Decode bit="27:16" name="L2DTlb4KSize" description="L2 data TLB number of entries for 4-KB pages." />
          <Decode bit="15:12" ValueDecode="AssociativityFields" name="L2ITlb4KAssoc" description="L2 instruction TLB associativity for 4-KB pages." />
          <Decode bit="11:0" name="L2ITlb4KSize" description="L2 instruction TLB number of entries for 4-KB pages." />
        </EBX>
        <ECX info="L2 Cache Identifiers" >
          <Decode bit="31:16" name="L2Size" description="L2 cache size in KB." />
          <Decode bit="15:12" ValueDecode="AssociativityFields" name="L2Assoc" description="L2 cache associativity." />
          <Decode bit="11:8" name="L2LinesPerTag" description="L2 cache lines per tag." />
          <Decode bit="7:0" name="L2LineSize" description="L2 cache line size in bytes." />
        </ECX>
        <EDX info="L3 Cache Identifiers" >
          <Decode bit="31:18" name="L3Size" description="Specifies the L3 cache size is within the following range: (L3Size[31:18] * 512KB) &lt;= L3 cache size &lt; ((L3Size[31:18]+1) * 512KB)." />
          <Decode bit="15:12" ValueDecode="AssociativityFields" name="L3Assoc" description="L3 cache associativity." />
          <Decode bit="11:8" name="L3LinesPerTag" description="L3 cache lines per tag." />
          <Decode bit="7:0" name="L3LineSize" description="L3 cache line size in bytes." />
        </EDX>
        <ValueDecode id="AssociativityFields" >
          <Value intput="0h" output="L2/L3 cache or TLB is disabled" />
          <Value intput="1h" output="Direct mapped" />
          <Value intput="2h" output="2-way associative" />
          <Value intput="4h" output="4-way associative" />
          <Value intput="6h" output="8-way associative" />
          <Value intput="8h" output="16-way associative" />
          <Value intput="Ah" output="32-way associative" />
          <Value intput="Bh" output="48-way associative" />
          <Value intput="Ch" output="64-way associative" />
          <Value intput="Dh" output="96-way associative" />
          <Value intput="Eh" output="128-way associative" />
          <Value intput="Fh" output="Fully associative" />
          <Defaut output="Reserved" />
        </ValueDecode>
      </Function>
      <Function input="8000_0007h">
        <EAX>
        </EAX>
        <EBX>
        </EBX>
        <ECX>
        </ECX>
        <EDX info="Advanced Power Management Information" >
          <Decode bit="8" name="TscInvariant" description="1 = The TSC rate is ensured to be invariant across all P-States, C-States, and stop grant transitions (such as STPCLK Throttling); therefore the TSC is suitable for use as a source of time. 0 = No such guarantee is made and software should avoid attempting to use the TSC as a source of time." />
          <Decode bit="7" name="HwPState" description="Hardware P-State control. [The P-State Current Limit Register] MSRC001_0061, [The P-State Control Register] MSRC001_0062, and [The P-State Status Register] MSRC001_0063 exist." />
          <Decode bit="6" name="100MhzSteps" description="100 Mhz multiplier control." />
          <Decode bit="5" name="STC" description="Software thermal control." />
          <Decode bit="4" name="TM" description="Hardware thermal control." />
          <Decode bit="3" name="TTP" description="THERMTRIP." />
          <Decode bit="2" name="VID" description="Voltage ID control." />
          <Decode bit="1" name="FID" description="Frequency ID control." />
          <Decode bit="0" name="TS" description="Temperature sensor." />
        </EDX>
      </Function>
      <Function input="8000_0008h">
        <EAX info="Address Size" >
          <Decode bit="23:16" name="GuestPhysAddrSize" description="Maximum guest physical byte address size in bits. This number applies only to guests using nested paging. When this field is zero, refer to the PhysAddrSize field for the maximum guest physical address size." />
          <Decode bit="15:8" name="LinAddrSize" description="Maximum linear byte address size in bits." />
          <Decode bit="7:0" name="PhysAddrSize" description="Maximum physical byte address size in bits. When GuestPhysAddrSize is zero, this field also indicates the maximum guest physical address size." />
        </EAX>
        <EBX>
        </EBX>
        <ECX info="Physical Core Count Information" >
          <Decode bit="15:12" name="ApicIdCoreIdSize[3:0]" description="Indicates the number of least significant bits in the Initial APIC ID that indicate CPU core ID within a processor. A zero value indicates that legacy methods must be used to derive the maximum number of cores. The size of this field determines the maximum number of cores (MNC) that the processor could theoretically support, not the actual number of cores that are actually implemented or enabled on the processor, as indicated by CPUID Fn8000_0008_ECX[NC]. if (ApicIdCoreIdSize[3:0] == 0){/*Used by legacy dual-core/single-core processors*/ MNC = CPUID Fn8000_0008_ECX[NC] + 1;} else {/*use ApicIdCoreIdSize[3:0] field*/ MNC = (2 ^ ApicIdCoreIdSize[3:0]);}" />
        </ECX>
        <EDX>
        </EDX>
      </Function>
      <Function input="8000_000Ah">
        <EAX info="SVM Revision" >
          <Decode bit="7:0" name="SvmRev" description="SVM revision." />
        </EAX>
        <EBX info="Feature Identification" >
          <Decode bit="31:0" name="NASID" description="Number of address space identifiers (ASID)." />
        </EBX>
        <ECX>
        </ECX>
        <EDX info="Feature Identification" >
          <Decode bit="9" name="Ssse3Sse5Dis" description="SSSE3 and SSE5 opcode set disable. Indicates support for MSR C001_1024[Ssse3Sse5Dis] to disable the SSSE3 and SSE5 instructions." />
          <Decode bit="3" name="NRIPS" description="NRIP save. Indicates support for NRIP save on #VMEXIT." />
          <Decode bit="2" name="SVML" description="SVM lock. Indicates support for SVM-Lock." />
          <Decode bit="1" name="LbrVirt" description="LBR virtualization. Support is provided for VMRUN to save and for VMEXIT to restore the following five MSRs: MSR0000_01D9 Debug Control Register (DBG_CTL_MSR), MSR0000_01DB Last Branch From IP Register (BR_FROM), MSR0000_01DC Last Branch To IP Register (BR_TO), MSR0000_01DD Last Exception From IP Register, MSR0000_01DE Last Exception To IP Register." />
          <Decode bit="0" name="NP" description="Nested paging." />
        </EDX>
      </Function>
      <Function input="8000_0019h">
        <EAX info="TLB 1GB Page Identifiers" >
          <Decode bit="31:28" ValueDecode="AssociativityFields" name="L1DTlb1GAssoc" description="L1 data TLB associativity for 1 GB pages." />
          <Decode bit="27:16" name="L1DTlb1GSize" description="L1 data TLB number of entries for 1 GB pages" />
          <Decode bit="15:12" ValueDecode="AssociativityFields" name="L1ITlb1GAssoc" description="L1 instruction TLB associativity for 1 GB pages." />
          <Decode bit="11:0" name="L1ITlb1GSize" description="L1 instruction TLB number of entries for 1 GB pages." />
        </EAX>
        <EBX info="TLB 1GB Page Identifiers" >
          <Decode bit="31:28" ValueDecode="AssociativityFields" name="L2DTlb1GAssoc" description="L2 data TLB associativity for 1 GB pages" />
          <Decode bit="27:16" name="L2DTlb1GSize" description="L2 data TLB number of entries for 1-GB pages." />
          <Decode bit="15:12" ValueDecode="AssociativityFields" name="L2ITlb1GAssoc" description="L2 instruction TLB associativity for 1-GB pages." />
          <Decode bit="11:0" name="L2ITlb1GSize" description="L2 instruction TLB number of entries for 1-GB pages." />
        </EBX>
        <ECX>
        </ECX>
        <EDX>
        </EDX>
        <ValueDecode id="AssociativityFields" >
          <Value intput="0h" output="L2/L3 cache or TLB is disabled" />
          <Value intput="1h" output="Direct mapped" />
          <Value intput="2h" output="2-way associative" />
          <Value intput="4h" output="4-way associative" />
          <Value intput="6h" output="8-way associative" />
          <Value intput="8h" output="16-way associative" />
          <Value intput="Ah" output="32-way associative" />
          <Value intput="Bh" output="48-way associative" />
          <Value intput="Ch" output="64-way associative" />
          <Value intput="Dh" output="96-way associative" />
          <Value intput="Eh" output="128-way associative" />
          <Value intput="Fh" output="Fully associative" />
          <Defaut output="Reserved" />
        </ValueDecode>
      </Function>
      <Function input="8000_0019h">
        <EAX info="Performance Optimization Identifiers" >
          <Decode bit="1" name="MOVU" description="MOVU SSE (multimedia) instructions are more efficient and should be preferred to SSE (multimedia) MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD." />
          <Decode bit="0" name="FP128" description="128-bit SSE (multimedia) instructions are executed with full-width internal operations and pipelines rather than decomposing them into internal 64-bit suboperations. This may impact how software performs instruction selection and scheduling." />
        </EAX>
        <EBX>
        </EBX>
        <ECX>
        </ECX>
        <EDX>
        </EDX>
      </Function>
    </Extended>
  </CPUID>
</AMD_features>